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56F8014_07 参数 Datasheet PDF下载

56F8014_07图片预览
型号: 56F8014_07
PDF下载: 下载PDF文件 查看货源
内容描述: 16位数字信号控制器 [16-bit Digital Signal Controllers]
分类和应用: 控制器
文件页数/大小: 125 页 / 2055 K
品牌: FREESCALE [ Freescale ]
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Register Descriptions  
5.6.8.1  
Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15—0  
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0  
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.  
5.6.9  
Fast Interrupt 0 Vector Address High Register (FIVAH0)  
Base + $8  
Read  
15  
0
14  
0
13  
0
12  
0
11  
0
10  
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
0
FAST INTERRUPT 0 VECTOR  
ADDRESS HIGH  
Write  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET  
Figure 5-11 Fast Interrupt 0 Vector Address High Register (FIVAH0)  
Reserved—Bits 15–5  
5.6.9.1  
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.  
5.6.9.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0  
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0  
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.  
5.6.10 Fast Interrupt 1 Match Register (FIM1)  
Base + $9  
Read  
15  
0
14  
0
13  
0
12  
0
11  
0
10  
0
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
0
0
0
FAST INTERRUPT 1  
Write  
0
0
0
0
0
0
0
0
0
0
0
0
RESET  
Figure 5-12 Fast Interrupt 1 Match Register (FIM1)  
5.6.10.1 Reserved—Bits 15–6  
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.  
5.6.10.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0  
These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service  
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table  
first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast  
Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority  
level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt.  
Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to  
the vector table.  
56F8014 Technical Data, Rev. 9  
Freescale Semiconductor  
Preliminary  
57  
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