5.6.4.4
Timer Channel 1 Interrupt Priority Level (TMR_1 IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.5
Timer Channel 0 Interrupt Priority Level (TMR_0 IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
2
5.6.4.6
I C Address Detect Interrupt Priority Level (I2C_ADDR IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.7
Reserved—Bits 3–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.5
Interrupt Priority Register 4 (IPR4)
Base + $4
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
ADC_ZC_LE
IPL
ADCB_CC
IPL
PWM_F IPL PWM_RL IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-7 Interrupt Priority Register 4 (IPR4)
Reserved—Bits 15–8
5.6.5.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
56F8014 Technical Data, Rev. 9
54
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
