Part 3 OCCS
3.1 Overview
This module provides the 2X system clock frequency to the System Integration Module (SIM), which uses
it to generate the various chip clocks. This module also produces the OSC_CLK signals plus the ADC
clock and high-speed peripheral clock.
The on-chip clock synthesis module allows product design using an internal relaxation oscillator to run
56F801X family parts at user-selectable frequencies up to 32MHz.
3.2 Features
The On-Chip Clock Synthesis (OCCS) module interfaces to the oscillator and PLL. The OCCS module
features:
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Internal relaxation oscillator
Ability to power down the internal relaxation oscillator
Ability to put the internal relaxation oscillator into a standby mode
3-bit postscaler provides control for the PLL output
Ability to power down the internal PLL
Provides 2X master clock frequency and OSC_CLK signals
Provides 3X fast peripheral clock to PWM and Timer
Safety shutdown feature is available in the event that the PLL reference clock disappears
Can be driven from an external clock source
The clock generation module provides the programming interface for both the PLL and internal relaxation
oscillator.
3.3 Operating Modes
In 56F801X family parts, either an internal oscillator or an external frequency source can be used to
provide a reference clock (SYS_CLK2) to the SIM.
The 2X system clock source output from the OCCS can be described by one of the following equations:
2X system frequency = oscillator frequency
2X system frequency = (oscillator frequency X 8) / (postscaler)
where:
postscaler = 1, 2, 4, 8, 16, or 32 PLL output divider
The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle
in the system clock output.
56F8014 Technical Data, Rev. 9
26
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
