56F8014 Signal Pins
Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
TDO
31
Output
Output
Test Data Output — This tri-stateable output pin provides a serial
disabled, output data stream from the JTAG/EOnCE port. It is driven in the
internal
pull-up
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
enabled
(GPIOD1)
Input/
Port D GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
After reset, the default state is TDO.
GPIOB0
(SCLK)
21
Input/
Output
Output
Port B GPIO — This GPIO pin can be individually programmed as
disabled, an input or output pin.
internal
pull-up
Input/
enabled,
SPI Serial Clock — In the master mode, this pin serves as an
Output
pin is in input output, clocking slaved listeners. In slave mode, this pin serves as
mode
the data clock input. A Schmitt trigger input is used for noise
immunity.
(SCL3)
Serial Data — This pin serves as the I2C serial clock.
Input/
Output
After reset, the default state is GPIOB0. The peripheral functionality
is controlled via the SIM. See Section 6.3.8.
3. This signal is also brought out on the GPIOB7 pin.
GPIOB1
1
Input/
Output
Port B GPIO — This GPIO pin can be individually programmed as
Output
disabled, an input or output pin.
internal
pull-up
(SS)
Input
enabled,
SPI Slave Select — SS is used in slave mode to indicate to the SPI
pin is in input module that the current transfer is to be received.
mode
(SDA4)
Serial Clock — This pin serves as the I2C serial data line.
Input/
Output
After reset, the default state is GPIOB1. The peripheral functionality
is controlled via the SIM. See Section 6.3.8.
4. This signal is also brought out on the GPIOB6 pin.
Return to Table 2-2
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
21
FREESCALE [ Freescale ]
