1
SS
(Input)
SS is held High on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
(Input)
tDV
Bits 14–1
MOSI
(Output)
Master MSB out
tF
Master LSB out
tR
Figure 10-7 SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tCL
tCH
tR
SCLK (CPOL = 1)
(Output)
tDS
tDH
MISO
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
(Input)
tDV(ref)
tDV
Bits 14– 1
MOSI
(Output)
Master MSB out
tF
Master LSB out
tR
Figure 10-8 SPI Master Timing (CPHA = 1)
56F8014 Technical Data, Rev. 9
102
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
