FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 28. Wake-Up Register Control Bits
LCTR3
LCTR2
LCTR1
LCTR0
L0 L1:L1 L2 Config
L2 L3:L3 L4 Config
x
x
x
x
x
0
1
0
1
0
0
1
1
x
x
x
x
0
1
0
1
x
x
x
x
Inputs Disabled
High Level Sensitive
Low Level Sensitive
Both Level Sensitive
–
–
x
x
x
0
Inputs Disabled
High Level Sensitive
Low Level Sensitive
Both Level Sensitive
0
1
1
x = Don’t care.
Table 29. Wake-Up Register Status Bits (59)
Name
Logic
Description
If bit = 1, wake-up occurred from Sleep or Stop modes; if bit = 0, no wake-up has
occurred.
L3WU
L2WU
L1WU
L0WU
0 or 1
0 or 1
0 or 1
0 or 1
When device is in Normal or Standby mode, bit reports the State on Lx pin (LOW
or HIGH) (0 = Lx LOW, 1 = Lx HIGH)
Notes
59. WUR status bits have two functions. After SBC wake-up, they indicate the wake up source; for example, L2WU set at logic [1] if wake-
up source is L2 input. After SBC wake-up and once the WUR register has been read, status bits indicate the real-time state of the Lx
inputs (1 = Lx is above threshold, 0 = Lx input is below threshold). If after a wake-up from Lx input a watchdog tomato occurs before the
first reading of the WUR register, the LxWU bits are reset. This can occur only if the SBC was in Stop mode.
TIMING REGISTER (TIM1/2)
Tables 30 through 34 contain the Timing Register information. The TIM register is composed of two sub registers:
• TIM1—Controls the watchdog timing selection as well as either the watchdog window or the watchdog time-out option
(Figure 28 and Figure 29, respectively). TIM1 is selected when bit D3 is 0 (Table 30). Watchdog timing characteristics are
described in Table 31.
• TIM2—Selects an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching the HS on
or off. TIM2 is selected when bit D3 is 1 (Table 32). Figure 30, page 49, describes HS operation when cyclic sense is selected
Cyclic sense timing characteristics are described in Table 34, page 49.
Both subregisters also report the CANL and TXD diagnostics.
Table 30. TIM1 Timing and CANL Failure Diagnostic Register
TIM1
R/W
D3
D2
D1
D0
$101b
W
R
–
0
WDW
WDT1
WDT0
TXPD
CANL2VDD
CANL2BAT
CANL2GND
Reset Value
–
–
0
0
0
Reset Condition
(Write) (60)
–
POR, RESET
POR, RESET
POR, RESET
Notes
60. See Table 13, page 42, for definitions of reset conditions.
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
FREESCALE [ Freescale ]
