FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
HIGH-SPEED CAN TRANSCEIVER MODES
The MODE bit (D0) controls the state of the CAN interface, TXRX or Sleep mode (Table 22). SC0 bit (D1) defines the slew
rate when the CAN module is in TXRX, and it controls the wake-up option (wake-up enable or disable) when the CAN module is
in Sleep mode.
Table 22. CAN High-Speed Transceiver Modes
CAN Mode
SC1
SC0
MODE
(Pass 1.1)
0
0
1
0
1
1
0
0
0
0
0
1
1
CAN TXRX, Slew Rate 0
CAN TXRX, Slew Rate 1
0
1
CAN TXRX, Slew Rate 2
1
CAN TXRX, Slew Rate 3
x
CAN Sleep and CAN Wake-Up Disable
CAN Sleep and CAN Wake-Up Enable
x
x = Don’t care.
Table 23. CAN Register Status Bits
Name
Logic
Description
No CAN wake-up occurred.
0
1
0
1
0
CANWU
CAN wake-up occurred.
No CAN failure.
CAN-F
CAN failure (55)
Identified CAN failure (55)
.
.
CAN-UF
Non-identified CAN failure.
1
0
1
No overtemperature or overcurrent on CANH or CANL drivers.
Overtemperature or overcurrent on CANH or CANL drivers.
THERM-CUR
Notes
55. Error bits are latched in the CAN register.
INPUT/OUTPUT REGISTER (IOR)
Tables 24 through 26 contain the Input/Output Register information. Table 25 provides information about information HS control
in Normal and Standby modes, while Table 26 provides status bit information.
Table 24. Input/Output Register
IOR
R/W
D3
D2
D1
D0
W
R
–
–
HSON
HSOT
0
–
–
$011b
V2LOW
VSUPLOW
DEBUG
Reset Value
–
–
–
–
–
–
Reset Condition
(Write) (56)
–
POR
Notes
56. See Table 13, page 42, for definitions of reset conditions.
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
FREESCALE [ Freescale ]
