FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 31. TIM1 Control Bits
WDW
WDT1
WDT0
Timing (ms typ)
Parameter
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
9.75
45
Watchdog Period 1
Watchdog Period 2
Watchdog Period 3
Watchdog Period 4
Watchdog Period 1
Watchdog Period 2
Watchdog Period 3
Watchdog Period 4
No Window Watchdog
100
350
9.75
45
Watchdog Window enabled
(Window length is half the
Watchdog Timing).
100
350
Window Closed
No Watchdog Clear Allowed
Window Open for Watchdog Clear
Window Open for Watchdog Clear
Watchdog Timing x 50%
Watchdog Period
Watchdog Timing x 50%
(Watchdog Timing Selected by TIM1 Bit WDW = 0)
Watchdog Period
(Watchdog Timing Selected by TIM1 Bit WDW=1)
Figure 29. Timeout Watchdog
Figure 28. Window Watchdog
Table 32. Timing Register Status Bits
Name
Logic
Failure Description
No CANL short to VDD.
0
1
0
1
0
1
0
1
CANL2VDD
CANL short to VDD.
No CANL short to VSUP.
CANL short to VSUP.
No CANL short to GND.
CANL short to GND.
No TXD dominant.
CANL2BAT
CANL2GND
TXPD
TXD dominant.
Table 33. TIM2 Timing and CANL Failure Diagnostic Register
TIM2
R/W
D3
D2
D1
D0
W
R
–
1
CSP2
CANL2BAT
0
CSP1
CANL2GND
0
CSP0
TXPD
$101b
CANL2VDD
Reset Value
Reset Condition (Write) (61)
Notes
–
–
0
–
POR, RESET
POR, RESET
POR, RESET
61. See Table 13, page 42, for definitions of reset conditions.
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
48
FREESCALE [ Freescale ]
