FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 36. LX2HS Control Bits
Logic
Wake-Up Inputs Supplied by HS
No.
Yes. Lx inputs sensed at sampling point.
0
1
Table 37. HSAUTO Control Bits
Logic
Auto-Timing HS in Sleep and Stop Modes
OFF.
ON, HS Cyclic, period defined in TIM2 subregister.
0
1
Table 38. CAN-INT Control Bits
Logic (63)
Description
Interrupt as soon as CAN bus failure detected.
0
1
Interrupt when CAN bus failure detected and fully identified.
Notes
63. If CAN-INT is at logic [0], any undetermined CAN failure will be latched in the CAN register (bit D1: CAN-UF) and can be accessed by
SPI (refer to CAN Register (CAN) on page 44). After reading the CAN register or setting CAN-INT to logic [1], it will be cleared
automatically. The existence of CAN-UF always has priority over clearing, meaning that a further undetermined CAN failure does not
allow clearing the CAN-UF bit.
Table 39. LPC Status Bits
Name
Logic
Failure Description
No CANH short to VDD.
CANH short to VDD.
0
1
0
1
0
1
0
1
CANH2VDD
No CANH short to VSUP.
CANH short to VSUP.
No CANH short to GND.
CANH short to GND.
CANH2BAT
CANH2GND
RXPR
No RXD permanent recessive.
RXD permanent recessive.
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
50
FREESCALE [ Freescale ]
