FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Cyclic Sense Timing,
ON Time
HS ON
Cyclic Sense Timing, OFF Time
HS OFF
HS
10 µs
Lx Sampling Point
Sample
time
Figure 30. HS Operation When Cyclic Sense Is Selected
Table 34. TIM2 Control Bits
Parameter
CSP2
CSP1
CSP0
Cyclic Sense Timing (ms)
Cyclic Sense/FWU Timing 1
Cyclic Sense/FWU Timing 2
Cyclic Sense/FWU Timing 3
Cyclic Sense/FWU Timing 4
Cyclic Sense/FWU Timing 5
Cyclic Sense/FWU Timing 6
Cyclic Sense/FWU Timing 7
Cyclic Sense/FWU Timing 8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4.6
9.25
18.5
37
74
95.5
191
388
LOW POWER CONTROL REGISTER (LPC)
Tables 35 through 39 contain the Low Power Control Register information. The LPC register controls:
• The state of HS in Stop and Sleep modes (HS permanently OFF or HS cyclic).
• Enable or disable of the forced wake-up function (SBC automatic wake-up after time spent in Sleep or Stop modes; time is
defined by the TIM2 sub register).
• Enable or disable the sense of the wake-up inputs (Lx) at the sampling point of the Cyclic Sense period (LX2HS bit). (Refer to
Reset Control Register (RCR) on page 44 for details of the LPC register setup required for proper cyclic sense or direct wake-
up operation.
The LPC register also reports the CANH and RXD diagnostic.
Table 35. Low Power Control Register
LPC
R/W
D3
D2
D1
D0
W
R
LX2HS
FWU
CAN-INT
HSAUTO
RXPR
$110b
CANH2VDD
CANH2BAT
CANH2GND
–
–
0
0
0
0
Reset Value
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
Reset Condition
(Write) (62)
Notes
62. See Table 13, page 42, for definitions of reset conditions.
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
FREESCALE [ Freescale ]
