FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SPI INTERFACE AND REGISTER DESCRIPTION
Table 13. Possible Reset Conditions
Condition
Name
Definition
Power-ON Reset
DATA FORMAT DESCRIPTION
Figure 27 illustrates an 8-bit byte corresponding to the
8 bits in a SPI register. The first three bits are used to identify
the internal SBC register address. Bit 4 is a read/write bit.
The last four bits are data sent from the MCU to the SBC or
read back from the 33742 to the MCU.
33742 Reset
POR
NR2R
33742 Mode
Transition
Normal Request to Reset Mode
Normal Request to Normal Mode
Normal Request to Standby Mode
Normal to Reset Mode
NR2N
NR2STB
N2R
The state of the MISO has no significance during the write
operation. However, during a read operation the final four bits
of MISO have meaning; namely, they contain the content of
the accessed register.
Standby to Reset Mode
STB2R
STO2R
STO2NR
RESET
Stop to Reset Mode
Stop to Normal Request
33742S in Reset Mode
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
33742 Mode
MISO
MOSI
A2
A1
A0 R/W D3
D2
D1
D0
REGISTER DESCRIPTIONS
The following tables in this section describe the SPI
register list and register bit meaning. Register reset values
are also described, along with the reset condition. A reset
condition is the condition causing the bit to be set at the reset
value.
Address
Data
Note Read operation: R/W bit = logic [0]
Write operation: R/W = logic [1]
:
Figure 27. Data Format Description.
Table 14. List of Registers
Comment and Use
Formal Name
and Link
Register
MCR
Address
$000
Write
Read
Selection for Normal, Standby, Sleep,
Stop, and Debug modes
BATFAIL, general failure, VDD pre-
warning, and Watchdog flag
Mode Control Register (MCR)
on page 43
Configuration for reset voltage level, CAN Sleep and Stop modes
RCR
$001
Reset Control Register (RCR)
on page 44
CAN slew rate, Sleep and Wake-Up
enable/disable modes, drive enable after
failure
CAN wake-up and CAN failure status bits
CAN
$010
CAN Register (CAN) on page
44
HS (high-side switch) control in Normal
and Standby mode
HS overtemperature bit, VSUP, and V2
LOW status
IOR
WUR
TIM
$011
$100
$101
Input/Output Register (IOR)
on page 45
Control of wake-up input polarity
Wake-up input and real time Lx input
state
on page 46
•
•
TIM1: Watchdog timing control, Watch-
dog Window (WDW) or Watchdog Tim-
eout (WTO) mode
CANL and TXD failure reporting
Timing Register (TIM1/2) on
page 47
TIM2: Cyclic Sense and Forced Wake-
Up timing selection
Control HS periodic activation in Sleep
and Stop modes, Forced Wake-Up mode
activation, CAN-INT mode selection
CANH and RXD failure reporting
Interrupt source
LPC
$110
$111
Low Power Control Register
(LPC) on page 49
Enable or Disable of Interrupts
INTR
Interrupt Register (INTR) on
page 51
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
42
FREESCALE [ Freescale ]
