ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
tPCLK
CS
tWSCLKH
tLEAD
tLAG
SCLK
tWSCLKL
tSISU
tSIH
MOSI
MISO
Undefined
tVALID
DI 0
Don’t Care
DI 8
Don’t Care
tSODIS
tSOEN
DO 0
DO 8
Note Incoming data at MOSI pin is sampled by the 33742 at SCLK falling edge. Outgoing data at MISO pin
is set by the 33742 at SCLK rising edge (after tVALID delay time).
Figure 7. SPI Timing Diagram
t
TRD
t
2.0 V
LRD
TXD
0.8 V
2.0 V
TXD
RXD
t
TDR
0.8 V
t
LDR
0.9 V
V
DIFF
0.5 V
2.0 V
VDIFF = VCANH - VCANL
0.8 V
Figure 8. Propagation Loop Delay TXD to RXD
Figure 9. Propagation Delay TXD to CAN
t
RDR
0.9 V
V
DIFF
0.5 V
t
RRD
2.0 V
RXD
0.8 V
Figure 10. Propagation Delay CAN to RXD
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FREESCALE [ Freescale ]
