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33742S 参数 Datasheet PDF下载

33742S图片预览
型号: 33742S
PDF下载: 下载PDF文件 查看货源
内容描述: 系统基础芯片( SBC)与增强型高速CAN收发器 [System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver]
分类和应用:
文件页数/大小: 65 页 / 1605 K
品牌: FREESCALE [ Freescale ]
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FUNCTIONAL DESCRIPTION  
INTRODUCTION  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
The 33742 and the 33742S are system basis chips (SBCs)  
dedicated to automotive applications. Their functions include  
the following:  
• Sleep and Stop modes low power operating modes to  
reduce an application’s current consumption while  
providing a wake-up capability from the CAN interface,  
L3:L0 wake-up inputs, or from a timer wake-up.  
• Programmable wake-up input and cyclic sense wake-  
ups.  
• CAN high-speed physical bus interface with TXD and  
RXD fault diagnostic capability and enhanced  
protection features.  
• One fully protected 5.0 V voltage regulator with 200 mA  
total output current capability available at the VDD pin.  
• VDD regulator undervoltage reset function,  
programmable window or time-out software watchdog  
function.  
• Internal driver (V2) for an external series pass transistor  
to implement a second 5.0 V voltage regulator.  
• Two running modes: Normal and Standby modes set by  
the system microcontroller.  
• An SPI interface for use in communicating with a MCU  
and Interrupt outputs to report SBC status, perform  
diagnostics, and report wake-up events.  
FUNCTIONAL PIN DESCRIPTION  
RECEIVE AND TRANSMIT DATA (RXD AND TXD)  
VOLTAGE SOURCE 2 (V2)  
The RXD and TXD pins (receive data and transmit data  
pins, respectively) are connected to a microcontroller’s CAN  
protocol handler. TXD is an input and controls the CANH and  
CANL line state (dominant when TXD is LOW, recessive  
when TXD is HIGH). RXD is an output and reports the bus  
state (RXD LOW when CAN bus is dominant, HIGH when  
CAN bus is recessive).  
The V2 pin is the input sense for the V2 regulator. It is  
connected to the external series pass transistor. V2 is also  
the 5.0 V supply of the internal CAN interface. It is possible to  
connect V2 to an external 5.0 V regulator or to the VDD  
output when no external series pass transistor is used. In this  
case, the V2CTRL pin must be left open. Refer to Figure 31,  
SBC Typical Application Schematic, page 52.  
Voltage Digital Drain (VDD)  
VOLTAGE SOURCE 2 CONTROL (V2CTRL)  
The VDD pin is the output pin of the 5.0 V internal  
regulator. It can deliver up to 200 mA. This output is protected  
against overcurrent and overtemperature. It includes an  
overtemperature pre-warning flag, which is set when the  
internal regulator temperature exceeds 130°C typical. When  
the temperature exceeds the overtemperature shutdown  
(170°C typical), the regulator is turned off.  
The V2CTRL pin is the output drive pin for the V2 regulator  
connected to the external series pass transistor.  
VOLTAGE SUPPLY (VSUP)  
The VSUP pin is the battery supply input of the device.  
HIGH-SIDE OUTPUT (HS)  
VDD includes an undervoltage reset circuitry, which sets  
the RST pin LOW when VDD is below the undervoltage reset  
threshold.  
The HS pin is the internal high-side driver output. It is  
internally protected against overcurrent and  
overtemperature.  
RESET OUTPUT (RST)  
LEVEL 0-3 INPUTS (L0: L3)  
The Reset pin RST is an output that is set LOW when the  
device is in reset mode. The RST pin is set HIGH when the  
device is not in reset mode. RST includes an internal pullup  
current source. When RST is LOW, the sink current capability  
is limited, allowing RST to be shorted to 5.0 V for software  
debug or software download purposes.  
The L0:L3 pins can be connected to contact switches or  
the output of other ICs for external inputs. The input states  
can be read by SPI. These inputs can be used as wake-up  
events for the SBC when operating in the Sleep or Stop  
mode.  
CAN HIGH AND CAN LOW OUTPUTS  
(CANH AND CANL)  
INTERRUPT OUTPUT (INT)  
The Interrupt pin INT is an output that is set LOW when an  
interrupt occurs. INT is enabled using the Interrupt Register  
(INTR). When an interrupt occurs, INT stays LOW until the  
interrupt source is cleared.  
The CAN High and CAN Low pins are the interfaces to the  
CAN bus lines. They are controlled by TXD input level, and  
the state of CANH and CANL is reported through RXD output.  
A 60 termination resistor is connected between CANH and  
CANL pins.  
INT output also reports a wake-up event by a 10 µs typical  
pulse when the device is in Stop mode.  
33742  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
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