ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE TIMING (SCLK, CS, MOSI, MISO) (28)
SPI Operation Frequency
fREQ
tPCLK
tWSCLKH
tWSCLKL
tLEAD
tLAG
0.25
250
125
125
100
100
40
—
—
—
—
—
—
—
—
4.0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MHz
ns
SCLK Clock Period
SCLK Clock High Time
ns
SCLK Clock Low Time
ns
Falling Edge of CS to Rising Edge of SCLK
Falling Edge of SCLK to Rising Edge of CS
MOSI to Falling Edge of SCLK
Falling Edge of SCLK to MOSI
ns
ns
tSISU
ns
tSIH
40
ns
MISO Rise Time (29)
CL = 220 pF
tRSO
ns
—
—
25
25
50
50
MISO Fall Time (29)
CL = 220 pF
tFSO
ns
ns
Time from Falling or Rising Edges of CS
MISO Low Impedance
tSOEN
tSODIS
—
—
—
—
50
50
MISO High Impedance
Time from Rising Edge of SCLK to MISO Data Valid
tVALID
ns
0.2 VDD ≤ MISO ≥ 0.8 VDD, CL = 200 pF
—
—
—
50
34
STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT)
Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop Mode Activation (30)
tCS-STOP
µs
µs
18
Interrupt Low-Level Duration
Stop Mode
tINT
7.0
—
10
13
—
Internal Oscillator Frequency (31)
fOSC
100
kHz
ms
Watchdog Period Normal and Standby Modes
tWDOG
Period 1
Period 2
Period 3
Period 4
8.58
39.6
88
9.75
45
10.92
50.4
112
100
350
308
392
Notes
28. See Figure 7, SPI Timing Diagram, page 21.
29. Not production tested. Guaranteed by design.
30. Not production tested. Guaranteed by design. Detected by V2 OFF.
31. fOSC is indirectly measured (1.0 ms reset) and trimmed.
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FREESCALE [ Freescale ]
