F81867
Select what protocol if a I2C transfer is triggered.
0001b: send byte.
0010b: write byte.
0011b: write word.
0100b: Reserved.
0101b: block write.
3-0
I2C_PROTOCOL
R/W 5VSB
0
0111b: quick command (write).
1001b: receive byte.
1010b: read byte.
1011b: Reserved
1101b: block read.
1111b: Reserved
Otherwise: reserved.
7.18.8.2 PECI 3.0 & Temperature Setting
PECI 3.0 Command and Register
PECI Configuration Register ⎯ Offset 40h
Bit
Name
R/W Reset Default
Description
When PECI temperature monitoring is enabled, set this bit 1 will
RDIAMSR_CMD_E
N
7
R/W
5VSB
0
0
generate
a
RdIAMSR() command before
a
GetTemp()
command.
If RDIAMSR_CMD_EN is not set to 1, the temperature data is
not allowed to be updated when the completion code of
RdIAMSR() is 0x82.
6
C3_UPDATE_EN R/W
Reserved
5VSB
-
5-4
3
R
-
Reserved
Set this bit 1 to enable updateing positive value of temperature if
the completion code of RdIAMSR() is 0x82.
C3_PTEMP_EN R/W 5VSB
0
Set this bit 1 to enable updating positive value of temperature if
the completion code of RdIAMSR() is not 0x82 and the bit 8 of
completion code is not 1 either.
Set this bit 1 to enable updating temperature value 0x0000 if the
completion code of RdIAMSR() is 0x82.
Set this bit 1 to enable updating temperature value 0x0000 if the
completion code of RdIAMSR() is not 0x82 and the bit 8 of
completion code is not 1 either.
2
1
0
C0_PTEMP_EN R/W 5VSB
0
0
0
C3_ALL0_EN
C0_ALL0_EN
R/W 5VSB
R/W 5VSB
PECI Master Control Register ⎯ Offset 41h
Bit
Name
R/W Reset
Default
Description
PECI_CMD_STAR
T
Write 1 to this bit to start a PECI command when using as a PECI
master. (PECI_PENDING must be set to 1)
7
W
R
5VSB
-
6-5
4
Reserved
-
5VSB
-
-
0
-
Reserved
PECI_PENDING R/W
Reserved
Set this bit 1 to stop monitoring PECI temperature.
Reserved
3
R
224
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
