F81866A
PECI Master DATA10 Register ⎯ Index 4Dh
Bit
Name
R/W Reset Default
R/W 5VSB
Description
7-0
PECI_DATA10
0
For RdIAMSR(), this byte represents “DATA[47:40]”.
PECI Master DATA11 Register ⎯ Index 4Eh
Bit
Name
R/W Reset Default
R/W 5VSB
Description
7-0
PECI_DATA11
0
For RdIAMSR(), this byte represents “DATA[55:48]”.
PECI Master DATA12 Register ⎯ Index 4Fh
Bit
Name
R/W Reset Default
R/W 5VSB
Description
7-0
PECI_DATA12
0
For RdIAMSR(), this byte represents “DATA[63:56]”.
HWM Manual Control Register ⎯ Index 50h
Bit
7
Name
R/W Reset Default
Description
LOAD_CH
STOP_CH
HOLD_CH
W
-
-
Write 1 to load a temperature or voltage channel to be converted
Set to 1 when load a channel will generate a one-shot conversion.
Set to 1 when load a channel will keep converting this channel.
6
R/W 5VSB
R/W 5VSB
0
0
5
First channel to be converted when LOAD_CH is set to 1.
00000: VCC
00001: VIN1
00010: VIN2
00011: VIN3
00100: VIN4
4:0
CHANNEL
R/W 5VSB
0
00101: VSB3V
00110: VBAT
00111: 5VSB
10000: Intel PECI
10001: T1
10010: T2
11000: AMD TSI/Intel IBEX
HWM Manual Control Status Register 1⎯ Index 51h
Bit
7
Name
Reserved
R/W Reset Default
Description
-
-
-
-
-
-
-
-
-
-
Reserved
6
V_CONV_STS
PECI_CONV_STS
TSI_CONV_STS
Reserved
R
5VSB
5VSB
5VSB
At least one of the voltage channels had finish converting.
PECI channel had finish converting
TSI channel had finish converting
Reserved
5
WC
WC
-
4
3
2
T2_CONV_STS
T1_CONV_STS
Reserved
WC
WC
-
5VSB
5VSB
T2 channel had finish converting
T1 channel had finish converting
Reserved
1
0
55
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
