F81866A
Temperature BEEP Enable Register ⎯ Index 63h
Bit
Name
R/W Reset Default
Description
7
Reserved
R/W
0
Reserved
-
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds OVT
6
5
EN_ T2_ OVT_BEEP R/W 5VSB
0
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds OVT
limit setting.
EN_ T1_ OVT_BEEP R/W 5VSB
EN_ T0_ OVT_BEEP R/W 5VSB
0
If set this bit to 1, BEEP signal will be issued when TEMP0 exceeds OVT
limit setting.
4
3
0
0
Reserved
R/W
-
Reserved
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds high
2
EN_ T2_EXC_BEEP R/W 5VSB
0
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds high
limit setting.
1
0
EN_ T1_EXC_BEEP R/W
0
0
5VSB
If set this bit to 1, BEEP signal will be issued when TEMP0 exceeds high
limit setting.
EN_ T0_EXC_BEEP R/W 5VSB
T1 OVT and High Limit Temperature Select Register ⎯ Index 64h
Bit
Name
R/W Reset Default
R/W Reserved
Description
7-6
Reserved
0
0
0
0
-
Select the source temperature for T1 OVT Limit.
0: Select T1 to be compared to Temperature 1 OVT Limit.
1: Select CPU temperature from PECI to be compared to Temperature 1
OVT Limit.
5-4
3-2
1-0
OVT_TEMP_SEL
R/W 5VSB
2: Select CPU temperature from AMD TSI or Intel PCH I2C to be
compared to Temperature 1 OVT Limit.
3: Select the MAX temperature from Intel PCH I2C to be compared to
Temperature 1 OVT Limit.
Reserved
R/W
-
Reserved
Select the source temperature for T1 High Limit.
0: Select T1 to be compared to Temperature 1 High Limit.
1: Select CPU temperature from PECI to be compared to Temperature 1
High Limit.
HIGH_ TEMP_SEL R/W
5VSB
2: Select CPU temperature from AMD TSI or Intel PCH I2C to be
compared to Temperature 1 High Limit.
3: Select the MAX temperature from Intel PCH I2C to be compared to
Temperature 1 High Limit.
58
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
