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F81866A 参数 Datasheet PDF下载

F81866A图片预览
型号: F81866A
PDF下载: 下载PDF文件 查看货源
内容描述: 6个UART超级IO 128字节FIFO和电源 [6 UARTs Super IO With 128 Bytes FIFO and Power]
分类和应用: 先进先出芯片
文件页数/大小: 210 页 / 1806 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F81866A  
Temperature Interrupt Status Register Index 61h  
Bit  
Name  
R/W Reset Default  
Description  
7
Reserved  
R/W  
0
Reserved  
-
This bit gets 1 to indicate TEMP2 temperature sensor has exceeded  
OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this bit,  
write 0 to ignore.  
6
5
T2_OVT _STS  
T1_OVT _STS  
R/W 3VCC  
R/W 3VCC  
0
This bit gets 1 to indicate TEMP1 temperature sensor has exceeded  
OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this bit,  
write 0 to ignore.  
0
A one indicates TEMP0 temperature sensor has exceeded OVT limit or  
below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be  
ignored.  
4
3
T0_OVT _STS  
Reserved  
R/W  
R/W  
3VCC  
-
0
0
Reserved  
This bit gets 1 to indicate TEMP2 temperature sensor has exceeded  
high limit or below the “high limit –hysteresis” limit. Write 1 to clear this  
bit, write 0 to ignore.  
2
T2_EXC _STS  
R/W 3VCC  
0
This bit gets 1 to indicate TEMP1 temperature sensor has exceeded  
high limit or below the “high limit –hysteresis” limit. Write 1 to clear this  
bit, write 0 to ignore.  
1
0
T1_EXC _STS  
T0_EXC _STS  
R/W  
R/W  
3VCC  
3VCC  
0
0
A one indicates TEMP0 temperature sensor has exceeded high limit or  
below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0  
will be ignored.  
Temperature Real Time Status Register Index 62h  
Bit  
Name  
R/W Reset Default  
Description  
7
Reserved  
R/W  
0
Reserved  
-
Set when the TEMP2 exceeds the OVT limit. Clear when the TEMP2 is  
below the “OVT limit –hysteresis” temperature.  
6
5
T2_OVT  
T1_OVT  
R/W 3VCC  
R/W 3VCC  
0
Set when the TEMP1 exceeds the OVT limit. Clear when the TEMP1 is  
below the “OVT limit –hysteresis” temperature.  
0
Set when the TEMP0 exceeds the OVT limit. Clear when the TEMP0 is  
below the “OVT limit –hysteresis” temperature.  
4
3
T0_OVT  
R/W  
R/W  
3VCC  
-
0
0
Reserved  
Reserved  
Set when the TEMP2 exceeds the high limit. Clear when the TEMP2 is  
below the “high limit –hysteresis” temperature.  
Set when the TEMP1 exceeds the high limit. Clear when the TEMP1 is  
below the “high limit –hysteresis” temperature.  
2
T2_EXC  
R/W 3VCC  
0
1
0
T1_EXC  
T0_EXC  
R/W  
R/W  
0
0
3VCC  
3VCC  
Set when the TEMP0 exceeds the high limit. Clear when the TEMP0 is  
below the “high limit –hysteresis” temperature.  
57  
Jan, 2012  
V0. 12P  
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