F81866A
6-5
4
Reserved
PECI_PENDING
Reserved
R
-
-
0
-
Reserved
R/W 5VSB
Set this bit 1 to stop monitoring PECI temperature.
Reserved
3
R
-
PECI command to be used by PECI master.
000: PING()
001: GetDIB()
010: GetTemp()
011: RdIAMSR()
2-0
PECI_CMD
R/W 5VSB
3’h0
100: RdPkgConfig()
101: WrPkgConfig()
others: Reserved
PECI Master Status Register ⎯ Index 42h
Bit
Name
R/W Reset Default
Description
7-3
Reserved
R
-
-
-
Reserved
This bit is the Abort FCS status of PECI master commands. Write this bit
1 or read this byte will clear this bit to 0.
2
1
0
ABORT_FCS
PECI_FCS_ERR
PECI_FINISH
R/WC 5VSB
R/WC 5VSB
R/WC 5VSB
This bit is the FCS error status of PECI master commands. Write this bit 1
or read this byte will clear this bit to 0.
-
-
This bit is the Command Finish status of PECI master commands. Write
this bit 1 or read this byte will clear this bit to 0.
PECI Master DATA0 Register ⎯ Index 43h
Bit
Name
R/W Reset Default
Description
For RdIAMSR(), RdPkgConfig() and WrPkgConfig() command, this byte
represents “Host ID[7:1] & Retry[0]”. Please refer to PECI interface
specification for more detail.
7-0
PECI_DATA0
R/W 5VSB
0
PECI Master DATA1 Register ⎯ Index 44h
Bit
Name
R/W Reset Default
Description
For RdIAMSR() , this byte represents “Processor ID”.
7-0
PECI_DATA1
R/W 5VSB
0
For RdPkgConfig() and WrPkgConfig() , this byte represents “Index”.
Please refer to PECI interface specification for more detail.
PECI Master DATA2 Register ⎯ Index 45h
Bit
Name
R/W Reset Default
Description
For RdIAMSR(), this byte is the least significant byte of “MSR Address”.
For RdPkgConfig() and WrPkgConfig(), this byte is the least significant
byte of “Parameter”.
7-0
PECI_DATA2
R/W 5VSB
0
Please refer to PECI interface specification for more detail.
53
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
