F81866A
Block Write Count Register – Index ECh
Bit
Name
R/W
Reset Default
Description
This bit is used to select the register in index E0h to E9h.
Set “0” to read the temperature bank and “1” to access the data bank.
Reserved
7
MCH_BANK_SEL
R/W
5VSB
-
0
0
0
6
Reserved
-
Use the register to specify the byte count of block write protocol. Support
up to 10 bytes.
5-0
BLOCK_WR_CNT
R/W
5VSB
I2C Command Byte/TSI Command Byte – Index EDh
Bit
Name
R/W
Reset Default
Description
There are actual two bytes for this index. TSI_CMD_PROG select which
byte to be programmed:
0: I2C_CMD, which is the command code for write byte/word, read
byte/word, block write/read and process call protocol.
1: TSI_CMD, which is the command code for Intel temperature interface
block read protocol and the data byte for AMD TSI send byte protocol.
7-0
I2C_CMD/TSI_CMD
R/W
5VSB
0/1
I2C Status – Index EEh
Bit
Name
R/W
Reset Default
Description
Set 1 to pending auto TSI accessing. (In AMD model, auto accessing will
issue a send-byte followed a receive-byte; In Intel model, auto accessing
will issue a block read).
7
TSI_PENDING
R/W
LRESET#
0
To use the SCL/ SDA as I2C master, set this bit to “1” first.
6
5
TSI_CMD_PROG
PROC_KILL
R/W
R/W
Set 1 to program TSI_CMD.
5VSB
5VSB
0
0
Kill the current I2C transfer and return the state machine to idle. It will set
a fail status if the current transfer is not completed.
This is set when PROC_KI LL kill an un-completed transfer. It will be
auto cleared by next I2C transfer.
4
3
2
1
0
FAIL_STS
I2C_ABT_ERR
I2C_TO_ERR
I2C_NAC_ERR
I2C_READY
R
R
R
R
R
5VSB
5VSB
5VSB
5VSB
5VSB
0
0
0
0
1
This is the arbitration lost status if I2C command is issued. Auto cleared
by next I2C command.
This is the timeout status if I2C command is issued. Auto cleared by next
I2C command.
This is the NACK error status if I2C command is issued. Auto cleared by
next I2C command.
0: I2C transfer is in process.
1: Ready for next I2C command.
51
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
