F81866A
HWM Manual Control Status Register 2⎯ Index 52h
Bit
7
Name
R/W Reset Default
Description
5VSB voltage channel had finish converting
VBAT voltage channel had finish converting
VSB3V voltage channel had finish converting
VIN4 voltage channel had finish converting
VIN3 voltage channel had finish converting
VIN2 voltage channel had finish converting
VIN1 voltage channel had finish converting
VCC voltage channel had finish converting
5VSB_CONV_STS
VBAT_CONV_STS
WC
WC
5VSB
5VSB
5VSB
5VSB
5VSB
5VSB
5VSB
5VSB
-
-
-
-
-
-
-
-
6
5
VSB3V_CONV_STS WC
4
VIN4_CONV_STS
VIN3_CONV_STS
VIN2_CONV_STS
VIN1_CONV_STS
VCC_CONV_STS
WC
WC
WC
WC
WC
3
2
1
0
HWM RAW Data Register 1⎯ Index 55h
Bit
Name
R/W Reset Default
5VSB
Description
7-0
RAW_DATA_L
R
0
Low byte of HM converting raw data
HWM RAW Data Register 2⎯ Index 56h
Bit
7-2
1-0
Name
Reserved
R/W Reset Default
Description
Reserved
-
-
-
RAW_DATA_H
R
5VSB
0
The highest two bits of HM converting raw data
Temperature Register
Temperature PME# Enable Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7
Reserved
R/W
0
Reserved
-
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds OVT
6
5
EN_ T2_OVT_PME R/W 5VSB
0
setting.
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds OVT
setting.
EN_ T1_OVT_PME R/W 5VSB
EN_ T0_ OVT_PME R/W 5VSB
0
If set this bit to 1, PME# signal will be issued when TEMP0 exceeds OVT
setting.
4
3
0
0
Reserved
R/W
-
Reserved
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds high
2
EN_ T2_EXC_PME R/W 5VSB
0
limit setting.
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds high
limit setting.
1
0
EN_ T1_EXC_PME R/W
0
0
5VSB
If set this bit to 1, PME# signal will be issued when TEMP0 exceeds high
limit setting.
EN_ T0_EXC_PME R/W 5VSB
56
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
