CMS4A16LAx–75Ex
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18 19
CLOCK
CKE
HIGH
*note 45.
tRC
/CS
/RAS
/CAS
tRP
tRCD
*note 46.
ADDR
BA0
RAa
CAa
RAb
CAb
BA1
A10/AP
CL=2
RAa
RAb
tOH
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
tRAC
*note 47.
tAC
tHZ *note 48.
tDPL
DQ
tOH
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
CL=3
tRAC
*note 47.
tAC
tHZ *note 48.
tDPL
/WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Don’t Care
Note :
45. Minimum row cycle times is required to complete internal DRAM operation.
46. Row precharge can interrupt burst on any cycle.[CAS Latency -1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t SHZ) after
the clock.
47. Access time from Row active command. tCLK *(tRCD + CAS latency - 1) + tAC
48. Out put will be Hi-Z after the end of burst. (1,2,3,8 & Full page bit burst)
Figure 11. Read & Write Cycle at Same Bank @Burst Length=4, tDPL = 1CLK (100Mhz) / tDPL = 2CLK (133Mhz)
28
Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
