CMS4A16LAx–75Ex
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18 19
CLOCK
CKE
HIGH
/CS
/RAS
*note 49.
/CAS
ADDR
RAa
RBb CAa
RCc CBb
RDd CCc
CDd
BA0
BA1
A10/AP
CL=2
RAa
RBb
RCc
RDd
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
DQ
CL=3
/WE
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(C-Bank)
Read
(D-Bank)
Precharge
(D-Bank)
Precharge
(C-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
Precharge
(A-Bank)
Precharge
(B-Bank)
Don’t Care
Note :
49. Row precharge will interrupt writing. Last data input, tDPL before Row precharge, will be written.
Figure 13. Page Read Cycle at Same Bank @ Burst Length=4
WRITE
in Figure 14. The starting column and bank addresses are
provided with the WRITE command, and auto precharge is
WRITE bursts are initiated with a WRITE command,as shown
30
Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
