XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
Registers 0x1B thru 0x1F unused.
REV. 1.0.1
TABLE 45: TRANSMIT
INTERFACE
C
ONTROL
REGISTER - E1 MODE
R
EGISTER 32 - E1 MODE
IT UNCTION
T
RANSMIT
I
NTERFACE
C
ONTROL EGISTER (TICR)
R
HEX ADDRESS:0X0120
B
F
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
TxSyncFrD
R/W
0
Tx Synchronous fraction data interface
0 = Fractional data Is clocked into the chip using TxChCLK
1 = Fractional data is clocked in to the chip using TxSerClk (ungapped).
TxChn[4:0] still indicates the time slot number if TxFr2048 is not 1,
TxIMODE[1:0] = 00, and TxMUXEN = 0. TxChClk is used as frac-
tional data
enable.
6
5
Reserved
-
-
Reserved
TxPLClkEnb
R/W
0
Tx payload clock enable
1 = TxSerClk will output Tx clock with OH bit period blocked in 2.048Hz
clock output mode.
TxSync is Low
TxFr2048
R/W
R/W
0
0
TxSync is Low
In H.100 and HMVIP Mode
0 = TxSync is active “Low”
1 = TxSync is active “High”
4
If TxMUXEN = 0 and TxIMODE[1:0] = 00
0 = TxChn[4:0] outputs the channel number as usual.
1 = TxChn[0]/TxSig inputs signaling information and TxChn[1]/TxFrTD
will input
fractional channel data in 2.048 Mbit mode.
Note; This bit has no effect while either TxMUXEN = 1 or TxIMODE[1:0]
= 00, TxChn[4:0] signals input TxSig and fractional data.
3
2
TxICLKINV
TxMUXEN
R/W
R/W
0
0
Clock Inversion
0 = Data transition happens on rising edge of the transmit clocks.
1 = Data transition happens on falling edge of the transmit clocks.
Mux Enable
0 = No channel multiplexing.
1 = Four channels are multiplexed in single serial stream.
63
EXAR [ EXAR CORPORATION ]
