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XRT86L30IV 参数 Datasheet PDF下载

XRT86L30IV图片预览
型号: XRT86L30IV
PDF下载: 下载PDF文件 查看货源
内容描述: 单一T1 / E1 / J1成帧器/ LIU COMBO [SINGLE T1/E1/J1 FRAMER/LIU COMBO]
分类和应用:
文件页数/大小: 284 页 / 1793 K
品牌: EXAR [ EXAR CORPORATION ]
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XRT86L30  
REV. 1.0.1  
SINGLE T1/E1/J1 FRAMER/LIU COMBO  
TABLE 43: GAPPED  
CLOCK  
CONTROL  
REGISTER  
R
EGISTER 30 - T1/E1  
UNCTION  
G
APPED LOCK ONTROL  
C
C
R
EGISTER (GCCR)  
HEX ADDRESS: 0X011E  
B
IT  
F
T
YPE  
D
EFAULT  
DESCRIPTION-OPERATION  
7
FrOutclk  
R/W  
0
Framer Output Clock Reference  
By default, the output clock reference on T1OSCCLK and  
E1OSCCLK output pins is 1.544MHz/2.048MHz respectively. By  
setting this bit to a “1”, the output clock reference is 49.408MHz/  
65.536MHz for T1/E1 respectively.  
0 = Standard T1/E1 Rate  
1 = High-Speed Rate  
[6:2] Reserved  
1 TxGCCR  
-
-
These bits are reserved  
R/W  
0
Transmit Gapped Clock Interface  
This bit is used to select a gapped clock interface operating at  
2.048Mbit/s in DS-1 mode. In this application, 63 gaps (missing  
data) are inserted so that the overall bit rate is reduced to 1.544Mbit/  
s. (In this mode, TxMSYNC is used as the 2.048MHz Gapped Clock  
Input. TxSER is used as the 2.048MHz Gapped Data Input.  
TxSERCLK must be 1.544MHz.)  
0 = Disabled  
1 = Transmit gapped clock for the Transmit Path  
0
RxGCCR  
R/W  
0
Receive Gapped Clock Interface  
This bit is used to select a gapped clock interface operating at  
2.048Mbit/s in DS-1 mode. In this application, 63 gaps (missing  
data) are inserted so that the overall bit rate is reduced to 1.544Mbit/  
s. (In this mode, RxSERCLK should be configured as an input so  
that a 2.048MHz Gapped Clock can be applied to the Framer block.  
RxSER is used as the 2.048MHz Gapped Data Output. The posi-  
tion of the gaps will be determined by the gaps placed in RxSER-  
CLK by the user.)  
0 = Disabled  
1 = Receive gapped clock for the Receive Path  
T
ABLE 44: GAPPED  
C
LOCK  
C
ONTROL  
R
EGISTER  
EX DDRESS: 0X011F  
R
EGISTER 31 - T1/E1  
MULTIPLEXED ()  
H
A
B
IT  
F
UNCTION YPE  
T
D
EFAULT  
DESCRIPTION-OPERATION  
7:2 Reserved  
R/W  
R/W  
-
Reserved  
1:0 MHSCCR[1:0]  
00  
Multiplexed High-Speed Channel Control  
These bits are used to select which channel (the channel position  
can be chosen from 1 of 4 different time slots) within the High-Speed  
serial data is to be processed by the framer. The other three chan-  
nels will be don’t care bits, since this is a single channel device.  
This allows the XRT86L30 to be compatible with High-Speed modes  
such as HMVIP/H.100, etc.  
00 = Channel 0  
01 = Channel 1  
10 = Channel 2  
11 = Channel 3  
62  
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