XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
TABLE 39: INTERRUPT
C
ONTROL
REGISTER
R
EGISTER 26
I
NTERRUPT
C
ONTROL
R
EGISTER (ICR)
HEX ADDRESS: 0X011A
B
IT
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7-3 Reserved
-
-
Reserved
Interrupt Write-to-Clear or Reset-upon-Read Select
2
INT_WC_RUR
R/W
0
Configures Interrupt Status bits to either Reset Upon Read or Write-
to-Clear
0=Interrupt Status bit RUR
1=Interrupt Status bit Write-to-Clear
1
0
ENBCLR
R/W
R/W
0
0
Interrupt Enable Auto Clear
0=Interrupt Enable bits are not cleared after status reading
1=Interrupt Enable bits are cleared after status reading
INTRUP_ENB
Interrupt Enable for Framer_n
Enables Framer n for Interrupt Generation.
0 = Disables corresponding framer block for Interrupt Generation
1 = Enables corresponding framer block for Interrupt Generation
TABLE 40: LAPD SELECT REGISTER
R
EGISTER 27
UNCTION
LAPD SELECT
R
EGISTER (LAPDSR)
H
EX
ADDRESS: 0X011B
B
IT
F
TYPE
D
EFAULT
D
ESCRIPTION-OPERATION
[7:2] Reserved
[1:0] LAPDsel
-
-
These bits are reserved
LAPD Select
R/W
0
Bits [1:0] determine which HDLC controller has access to the Read/
Write registers 0x0600 and 0x0700 for storing or extracting LAPD
messages.
00 = HDLC Controller 1
01 = HDLC Controller 2
10 = HDLC Controller 3
11 = HDLC Controller 1
60
EXAR [ EXAR CORPORATION ]
