XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
T
ABLE 47: RECEIVE
I
NTERFACE
C
ONTROL
R
EGISTER (RICR) - E1 MODE
EGISTER (RICR)
Register 33 - E1 Mode
RECEIVE NTERFACE
I
C
ONTROL
R
0X0122
B
IT
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
1
RxIMODE[1]
RxIMODE[0]
R/W
R/W
0
0
Rx Intf Mode Selection
This mode selection determines the interface speed.
When RxMUXEN = 0
0
00 = Receive interface is presenting data at a rate of 2.048Mbit/s.
01 = Receive interface is presenting data at a rate of 2.048Mbit/s.
10 = Receive interface is presenting data at a rate of 4.096Mbit/s.
11 = Receive interface is presenting data at a rate of 8.192Mbit/s.
When RxMUXEN = 1
00 = Reserved
01 = Receive interface is taking data from the four LIU input channels 0
through 3 and byte-multiplexing into the serial output channel 0. The TxSYNC
pulse remains “High” during the framing bit of each E1 frame.
10 = Receive interface is taking data from the four LIU input channels 0
through 3 and byte-multiplexing into the serial output channel 0 (HMVIP
Mode). The TxSYNC pulse remains “High” during the last two bits of the pre-
vious E1 frame and the first two bits of the current E1 frame.
11 = Receive interface is taking data from the four LIU input channels 0
through 3 and byte-multiplexing into the serial output channel 0 (H.100 Mode).
The TxSYNC pulse remains “High” during the last bit of the previous E1 frame
and the first bit of the current E1 frame.
NOTE: Channels 4 through 7 are multiplexed into the serial output at channel
4.
T
ABLE 48: RECEIVE
I
NTERFACE
C
ONTROL
R
EGISTER (RICR) - T1 MODE
EGISTER (RICR)
Register 33 - T1 Mode
R
ECEIVE
INTERFACE
C
ONTROL
R
0X0122
B
IT
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
RxSyncFrD
R/W
0
Rx synchronous fractional data interface
1 = RxChClk is used to output fractional data instead of being fraction data
clock. In this
mode, fractional data is clocked out of the chip using RxSerClk
(ungapped). RxChn
still indicates the time slot number if RxFr1544 is not 1, RxIMODE[1:0] =
00, and
RxMUXEN = 0.
RxCClk will be a valid signal for fractional data output (RxFrTD) if RxFr1544 is
1 or RxIMODE[1:0] = 00 or RxMUXEN = 0
6
5
Reserved
-
-
Reserved
RxPLClkEnb/
R/W
0
Rx Payload Clock Enable
1 = RxSerClk will output Rx clock with OH bit period blocked while in
1.544MHz clock
output mode.
RxSyncislow
RxSync is low
In H.100 and HMVIP Mode
1 =Rx Sync active low.
0 = RxSync active high.
67
EXAR [ EXAR CORPORATION ]
