XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
TABLE 37: DMA 0 (WRITE) CONFIGURATION
R
EGISTER
R
EGISTER 24
DMA 0 WRITE
C
ONFIGURATION
R
EGISTER (D 0 WCR)
HEX ADDRESS: 0X0118
B
IT
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
2
1
0
DMA0_CHAN(2)
DMA0_CHAN(1)
DMA0_CHAN(0)
R/W
R/W
R/W
0
0
0
Channel Select
Selects which channel, within the chip, is to use the DMA_0 (Write)
interface.
000 = Channel 0
001 = Channel 1
001 = Channel 2
011 = Channel 3
100 = Channel 4
101 = Channel 5
110 = Channel 6
111 = Channel 7
TABLE 38: DMA 1 (READ) CONFIGURATION
REGISTER
R
EGISTER 25
DMA 1 (READ) CONFIGURATION EGISTER (D1CR)
R
H
EX
ADDRESS: 0X0119
B
IT
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7-6 Reserved
-
-
Reserved
DMA_1 Reset
7
6
5
DMA1 RST
DMA1 ENB
RD TYPE
R/W
0
Resets the DMA 1 Channel
0 = Normal operation.
1 = A zero to one transition resets DMA channel.
R/W
R/W
0
0
DMA1_ENB
Enables DMA_1 interface
0 = Disables DMA_1 interface
1 = Enables DMA_1 interface
Selects the function of pRD_L signal.
0 = RD functions as a Read Strobe signal
11 = RD acts as a direction signal, WR works as a data strobe.
4 - 3 Reserved
-
-
Reserved
2
1
0
DMA1_CHAN(2)
R/W
R/W
R/W
0
0
0
Channel Select
Selects which channel, within the chip, is to use the DMA_1 inter-
face.
DMA1_CHAN(1)
DMA1_CHAN(0)
000 = Channel 0
001 = Channel 1
001 = Channel 2
011 = Channel 3
100 = Channel 4
101 = Channel 5
110 = Channel 6
111 = Channel 7
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