XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
T
ABLE 47: RECEIVE
I
NTERFACE
C
ONTROL
R
EGISTER (RICR) - E1 MODE
EGISTER (RICR)
Register 33 - E1 Mode
R
EFAULT
0
ECEIVE NTERFACE
I
C
ONTROL
R
0X0122
B
IT
F
UNCTION
T
YPE
D
DESCRIPTION-OPERATION
7
RxSyncFrD
R/W
Rx synchronous fractional data interface
0 = Fractional data is clocked out from the chip using RxChCLK
1 = RxChClk is used to output fractional data enable instead of being fraction
data clock. In this mode, fractional data is clocked out of the chip using
RxSerClk (ungapped). RxChn still indicates the time slot number if RxFr2048
is not 1, RxIMODE[1:0] = 0, and RxMUXEN = 0.
6
5
Reserved
-
-
Reserved
RxPLClkEnb/
R/W
0
Rx Payload Clock Enable
1 = RxSerClk outputs Rx clock with OH bit period blocked while in 2.048MHz
clock
output mode.
RxSyncislow
RxFr2048
RxSync is low
In H.100 and HMVIP Mode
1 = RxSync active low.
0 = RxSync active high.
4
R/W
0
Clock Inversion
1 = RxChn[0]/RxSig outputs signaling information, RxChn[1]/RxFrTD will out-
put
fractional channel data in 2.048 MHz mode and RxChn[2] will output the
serial
channel number of each time slot.
0 = RxChn[4:0] outputs the parallel channel number as usual.
3
2
RxICLKINV
RxMUXEN
N/A
0
0
Clock Inversion
0 = Data transition happens on the rising edge of the transmit clocks.
1 = Data transition happens on the falling edge of the transmit clocks.
R/W
Mux Enable
0 = No channel Multiplexing.
1 = Four channels are multiplexed in single serial stream.
66
EXAR [ EXAR CORPORATION ]
