XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
TABLE 35: SLIP
B
UFFER
C
ONTROL
REGISTER
R
EGISTER 22
S
LIP
B
UFFER
C
ONTROL
R
EGISTER (SBCR)
HEX ADDRESS: 0X0116
B
IT
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
1
0
SB_ENB(1)
SB_ENB(0)
R/w
0
0
Slip Buffer Mode Select
Selects mode of operation of slip buffer.
R/W
00 = Buffer is bypassed and RxSync and RxSERClk are outputs.
01 = Elastic store slip buffer enabled. RxSERClk is an input.
10 = Buffer acts as FIFO Data latency dictated by the setting within
the FIFO
Latency Register. RxSERClk is an input.
11 = Buffer is bypassed. RxSync and RxSERClk are outputs.
TABLE 36: FIFO LATENCY REGISTER
R
EGISTER 23
IT
FIFO LATENCY
R
EGISTER (FFOLR)
HEX ADDRESS: 0X0117
B
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7-5 Reserved
4-0 Latency
-
-
Reserved
R/W
0
Sets the distance between slip buffer read and slip buffer write point-
ers in FIFO mode.
TABLE 37: DMA 0 (WRITE) CONFIGURATION
R
EGISTER
R
EGISTER 24
DMA 0 WRITE
C
ONFIGURATION
R
EGISTER (D 0 WCR)
HEX ADDRESS: 0X0118
B
IT
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
6
5
DMA0 RST
DMA0 ENB
WR TYPE
R/W
R/W
R/W
0
DMA_0 Reset
Resets transmit DMA 0 channel.
0 = Normal operation.
1 = A zero to one transition resets DMA channel_0.
0
0
DMA_0 Enable
Enables DMA_0 interface.
0 = Disables DMA_0 interface
1 = Enables DMA_0 interface
Write Type Select
Selects function of WR signal.
0 = WR functions as direction signal (indicates whether the current
bus
cycle is a read or write operation) and RD functions as a data
strobe
signal.
1 = WR functions as a write strobe signal and RD functions as con-
figured in
the DMA 1 configuration register.
4 - 3 Reserved
-
-
Reserved
58
EXAR [ EXAR CORPORATION ]
