XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
TABLE 34: RECEIVE
D
ATA
L
INK
B
YTE
COUNT REGISTER
R
EGISTER 21
IT
R
ECEIVE
D
ATA
L
INK
B
YTE OUNT
C
R
EGISTER 1 (RDLBCR1)
HEX ADDRESS: 0X0115
B
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
RBUFPTR
R/W
0
Receive HDLC1 Buffer-Pointer
Identifies which RxHDLC1 buffer contains the newly received
HDLC1 message.
0 = HDLC1 message is stored in Rx HDLC1 Buffer 0.
1 = HDLC1 message is stored in Rx HDLC1 Buffer 1.
6
5
4
3
2
1
0
RDLBC6
RDLBC5
RDLBC4
RDLBC3
RDLBC2
RDLBC1
RDLBC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Receive HDLC Message - byte count
In MOS Mode
These seven bit-fields contain the size in bytes of the HDLC1 mes-
sage that has been extracted and written into the Rx HDLC1 buffer.
In BOS Mode
These bits should be set to the value of the message repetitions
before each receive interrupt. If they are set to “0”, no RxEOT inter-
rupt will be generated.
TABLE 35: SLIP
B
UFFER
C
ONTROL
REGISTER
R
EGISTER 22
S
LIP
B
UFFER
C
ONTROL
R
EGISTER (SBCR)
HEX ADDRESS: 0X0116
B
IT
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
TxSB_ISFIFO
R/W
0
Selects slip buffer as a FIFO for all clock modes while TxClk and
TxSerClk are synced.
0 = Buffer acts as slip buffer if enabled.
1 = Buffer acts as a FIFO. The data latency is dictated by FIFO
Latency.
6-5 Reserved
-
-
Reserved
4
3
2
SB_FORCESF
R/W
0
Force Signaling Freeze
Setting this bit “High” stops further signal updating until this bit is
cleared.
1 = Signaling array is not updated.
0 = Signaling array is updated only if SB_ENB[1:0] = 01 or 10
SB_SFENB
SB_SDIR
R/W
R/W
0
1
Signal Freeze Enable
This bit enables signaling freeze for one multiframe after buffer slip-
ping.
1 = Signaling freeze is enabled.
0 = Signaling freeze is disabled.
Slip Buffer (RxSync) Direction Select
Allows RxSync output pin to be an input or an output.
0 = RxSync is an output pin
1 = RxSync is an input pin
57
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