XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
TABLE 147: MICROPROCESSOR REGISTER #560 BIT DESCRIPTION
D3
NLCDIE_n Network Loop-Code Detection Interrupt Enable: Writing a
“1” to this bit enables Network Loop-code detection interrupt
generation, writing a “0” masks it.
R/W
0
0
0
0
D2
D1
D0
AISDIE_n
AIS Interrupt Enable: Writing a “1” to this bit enables Alarm
Indication Signal detection interrupt generation, writing a “0”
masks it.
R/W
R/W
R/W
RLOSIE_n Receive Loss of Signal Interrupt Enable: Writing a “1” to this
bit enables Loss of Receive Signal interrupt generation, writing
a “0” masks it.
QRPDIE_n QRSS Pattern Detection Interrupt Enable: Writing a “1” to
this bit enables QRSS pattern detection interrupt generation,
writing a “0” masks it.
TABLE 148: MICROPROCESSOR
REGISTER #561 BIT DESCRIPTION
R
EGISTER ADDRESS
C
HANNEL_0
R
EGISTER
R
VALUE
ESET
0X0F05H
FUNCTION
TYPE
Bit #
D7
NAME
Reserved
DMO_n
RO
RO
0
0
D6
Driver Monitor Output: This bit is set to a “1” to indicate
transmit driver failure is detected. The value of this bit is based
on the current status of DMO for the corresponding channel. If
the DMOIE bit is enabled, any transition on this bit will gener-
ate an Interrupt.
D5
D4
FLS_n
LCV_n
FIFO Limit Status: This bit is set to a “1” to indicate that the jit-
ter attenuator read/write FIFO pointers are within +/- 3 bits. If
the FLSIE bit is enabled, any transition on this bit will generate
an Interrupt.
RO
RO
0
0
Line Code Violation: This bit is set to a “1” to indicate that the
receiver of channel n is currently detecting a Line Code Viola-
tion or an excessive number of zeros in the B8ZS or HDB3
modes. If the LCVIE bit is enabled, any transition on this bit will
generate an Interrupt.
128
EXAR [ EXAR CORPORATION ]
