XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
TABLE 146: MICROPROCESSOR REGISTER #559 BIT DESCRIPTION
D4
RXRES1_n Receive External Resistor Control Pin 1: In Host mode, this bit
along with the RXRES0_n bit selects the value of the external
Receive fixed resistor according to the following table;
R/W
0
Required Fixed External
RXRES1_n
RXRES0_n
RX Resistor
No external Fixed
Resistor
0
0
1
1
0
1
0
1
240
210
150
Ω
Ω
Ω
D3
D2
RXRES0_n Receive External Resistor Control Pin 0: For function of this bit
see description of D4 the RXRES1_n bit.
R/W
R/W
0
0
INSBPV_n Insert Bipolar Violation: When this bit transitions from “0” to
“1”, a bipolar violation is inserted in the transmitted data
stream of the selected channel number n. Bipolar violation can
be inserted either in the QRSS pattern, or input data when
operating in single-rail mode. The state of this bit is sampled
on the rising edge of the respective TCLK_n.
NOTE
:
To ensure the insertion of a bipolar violation, a “0”
should be written in this bit location before writing a
“1”.
D1
D0
INSBER_n Insert Bit Error: With TDQRSS enabled, when this bit transi-
tions from “0” to “1”, a bit error will be inserted in the transmit-
ted QRSS pattern of the selected channel number n. The state
of this bit is sampled on the rising edge of the respective
TCLK_n.
R/W
0
0
NOTE
:
To ensure the insertion of bit error, a “0” should be
written in this bit location before writing a “1”.
Reserved
This Bit Is Not Used
R/W
TABLE 147: MICROPROCESSOR
REGISTER #560 BIT DESCRIPTION
R
EGISTER ADDRESS
C
HANNEL_0
R
EGISTER
R
VALUE
ESET
0X0F04H
FUNCTION
TYPE
Bit #
D7
NAME
Reserved
DMOIE_n
This Bit Is Not Used
RO
0
0
D6
DMO Interrupt Enable: Writing a “1” to this bit enables DMO
R/W
interrupt generation, writing a “0” masks it.
D5
D4
FLSIE_n
LCVIE_n
FIFO Limit Status Interrupt Enable: Writing a “1” to this bit
enables interrupt generation when the FIFO limit is within to 3
bits, writing a “0” to masks it.
R/W
R/W
0
0
Line Code Violation Interrupt Enable: Writing a “1” to this bit
enables Line Code Violation interrupt generation, writing a “0”
masks it.
127
EXAR [ EXAR CORPORATION ]
