XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
TABLE 148: MICROPROCESSOR
R
EGISTER #561 BIT
DESCRIPTION
D3
NLCD_n
Network Loop-Code Detection:
RO
0
This bit operates differently in the Manual or the Automatic
Network Loop-Code detection modes.
In the Manual Loop-Code detection mode, (NLCDE1 = “0”
and NLCDE0 = “1” or NLCDE1 = “1” and NLCDE0 = “0”) this
bit gets set to “1” as soon as the Loop-Up (“00001”) or Loop-
Down (“001”) code is detected in the receive data for longer
than 5 seconds. The NLCD bit stays in the “1” state for as long
as the chip detects the presence of the Loop-code in the
receive data and it is reset to “0” as soon as it stops receiving
it. In this mode, if the NLCD interrupt is enabled, the chip will
initiate an interrupt on every transition of the NLCD.
When the Automatic Loop-code detection mode, (NLCDE1
= “1” and NLCDE0 =”1”) is initiated, the state of the NLCD
interface bit is reset to “0” and the chip is programmed to mon-
itor the receive input data for the Loop-Up code. This bit is set
to a “1” to indicate that the Network Loop Code is detected for
more than 5 seconds. Simultaneously the Remote Loop-Back
condition is automatically activated and the chip is pro-
grammed to monitor the receive data for the Network Loop
Down code. The NLCD bit stays in the “1” state for as long as
the Remote Loop-Back condition is in effect even if the chip
stops receiving the Loop-Up code. Remote Loop-Back is
removed if the chip detects the “001” pattern for longer than 5
seconds in the receive data.Detecting the “001” pattern also
results in resetting the NLCD interface bit and initiating an
interrupt provided the NLCD interrupt enable bit is active.
When programmed in Automatic detection mode, the
NLCD interface bit stays “High” for the entire time the Remote
Loop-Back is active and initiate an interrupt anytime the status
of the NLCD bit changes. In this mode, the Host can monitor
the state of the NLCD bit to determine if the Remote Loop-
Back is activated.
D2
D1
D0
AISD_n
RLOS_n
QRPD_n
Alarm Indication Signal Detect: This bit is set to a “1” to indi-
cate All Ones Signal is detected by the receiver. The value of
this bit is based on the current status of Alarm Indication Signal
detector of channel n. If the AISDIE bit is enabled, any transi-
tion on this bit will generate an Interrupt.
RO
RO
RO
0
0
0
Receive Loss of Signal: This bit is set to a “1” to indicate that
the receive input signal is lost. The value of this bit is based on
the current status of the receive input signal of channel n. If the
RLOSIE bit is enabled, any transition on this bit will generate
an Interrupt.
Quasi-random Pattern Detection: This bit is set to a “1” to
indicate the receiver is currently in synchronization with QRSS
pattern. The value of this bit is based on the current status of
Quasi-random pattern detector of channel n. If the QRPDIE bit
is enabled, any transition on this bit will generate an Interrupt.
129
EXAR [ EXAR CORPORATION ]
