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ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
REV. 4.2.0
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R1
0-120
(Optional)
R2
500K - 1M
1.8432 MHz
to
Y1
24 MHz
C1
C2
22-47pF
22-47pF
2.4
Programmable Baud Rate Generator
The UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a software
bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external clock by
1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a
programmable divisor between 1 and (216 -1) to obtain a 16X sampling clock of the serial data rate. The
sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor
(DLL and DLM registers) defaults to a random value upon power up or a reset. Therefore, the BRG must be
programmed during initialization to the operating data rate. Programming the Baud Rate Generator Registers
DLM and DLL provides the capability of selecting the operating data rate. Table 2 shows the standard data
rates available with a 14.7456 MHz crystal or external clock at 16X clock rate. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
9
EXAR [ EXAR CORPORATION ]
