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ST16C1550IJ28 参数 Datasheet PDF下载

ST16C1550IJ28图片预览
型号: ST16C1550IJ28
PDF下载: 下载PDF文件 查看货源
内容描述: 具有16字节FIFO 2.97V至5.5V UART [2.97V TO 5.5V UART WITH 16-BYTE FIFO]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片数据传输时钟
文件页数/大小: 37 页 / 403 K
品牌: EXAR [ EXAR CORPORATION ]
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ST16C1550/51  
2.97V TO 5.5V UART WITH 16-BYTE FIFO  
áç  
REV. 4.2.0  
TABLE 2: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK  
DLM  
PROGRAM  
VALUE (HEX) VALUE (HEX)  
DLL  
PROGRAM  
DATA RATE  
ERROR (%)  
OUTPUT Data Rate OUTPUT Data Rate DIVISOR FOR 16x DIVISOR FOR 16x  
MCR Bit-7=1  
MCR Bit-7=0  
Clock (Decimal) Clock (HEX)  
100  
600  
400  
2304  
384  
192  
96  
48  
24  
12  
6
900  
180  
C0  
60  
09  
01  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
80  
C0  
60  
30  
18  
0C  
06  
04  
02  
01  
0
0
0
0
0
0
0
0
0
0
0
2400  
1200  
2400  
4800  
9600  
19.2k  
38.4k  
57.6k  
115.2k  
230.4k  
4800  
9600  
19.2k  
38.4k  
76.8k  
153.6k  
230.4k  
460.8k  
921.6k  
30  
18  
0C  
06  
4
04  
2
02  
1
01  
2.5  
Transmitter  
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which  
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal  
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,  
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in  
the Line Status Register (LSR bit-5 and bit-6).  
2.5.1  
Transmit Holding Register (THR) - Write Only  
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host  
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,  
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input  
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write  
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data  
location.  
2.5.2  
Transmitter Operation in non-FIFO Mode  
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the  
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled  
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.  
10  
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