ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
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REV. 4.2.0
3.0 UART INTERNAL REGISTERS
The 155X has a set of configuration registers selected by address lines A0, A1 and A2. The 16C550
compatible registers can be accessed when LCR[7] = 0 and the baud rate generator divisor registers can be
accessed when LCR[7] = 1. The complete register set is shown on Table 3 and Table 4.
TABLE 3: ST16C155X UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES
REGISTER
READ/WRITE
COMMENTS
0
0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0
0
0
0
0 0
0 1
0 1
1 0
DLL - Div Latch Low Byte
DLM - Div Latch High Byte
IER - Interrupt Enable Register
Read/Write
Read/Write
Read/Write
LCR[7] = 1
LCR[7] = 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0
1
1
1 1
0 0
0 1
LCR - Line Control Register
Read/Write
Read/Write
MCR - Modem Control Register
LSR - Line Status Register
Reserved
Read-only
Write-only
LCR[7] = 0
1
1
1 0
1 1
MSR - Modem Status Register
Reserved
Read-only
Write-only
SPR - Scratch Pad Register
Read/Write
14
EXAR [ EXAR CORPORATION ]
