Table 6-19. PLL Signal Interface
Signal Name
I/O Type
Description
prefclk
Input
System Reference Clock (25 or 125 MHz). Gigabit mode is
supported with a either a 25MHz or 125MHz reference
clock for GMII/TBI, RGMII/RTBI. In Serdes and SGMII
mode, this signal must have a differential 125Mhz
reference and requires a pull-down resistor.
pll_bypass
Input
Input
PLL Bypass Mode. Must be tied low for normal operation.
Tie high for Hifn test mode.
pll_mode[1]
PLL Modes: Selects between 25MHz and 125MHz input
reference clock.
0 = 125MHz input reference clock
1 = 25Mhz input reference clock
6.6 JTAG Interface
The 4450 provides an IEEE 1149.1 JTAG interface for boundary scan. This feature helps test
the interface of the chip during manufacturing tests, and the connection to the customer
board during diagnostic tests. The JTAG interface signals are all referenced to supply
voltage VDDE.
Table 6-20. JTAG Signal Interface
Signal Name
jtag_tck
I/O Type
Input
Description
JTAG test clock
jtag_tdi
Input
JTAG test data input
JTAG test data output
JTAG test mode select.
jtag_tdo
Output
Input
jtag_tms
jtag_rst_n
Input
JTAG test reset This should not be tied to the system reset
signal. It is normally tied low at all times except during
JTAG testing.
Table 6-21 below lists the JTAG IDs for each revision of the chip.
Table 6-21. JTAG Chip and Revision IDs
Model
4450
4450
JTAG ID
Revision ID
0x02
0x2CCB74AD
0x3CCB74AD
0x03
6.7 General Purpose Pins
There are two banks of eight General Purpose I/O pins for both the eSC and DPU
processors. All pins default to input following reset, therefore all GPIO pins must be
terminated to a known state. Internal registers accessed by the eSC and DPU processors
control the I/O direction of each pin. The GPIO pins may have pre-defined primary or
secondary (Reset Capture) uses as described below and summarized in Table 6-22. The
4450 – Data Sheet, DS-0131-06
Page57
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