• the Hifn IKE is going to run on the eSC (64 MBytes should be allowed for IKE.)
• a Non-IKE eSC image is needed (Generally, 32 MBytes of external SDRAM is an
adequate allowance for a non-IKE image)
• more than the maximum number of internal SAs are required (An approximation of
required memory for SA storage is 220 bytes per SA entry)
Additional details regarding memory sizing requirements will be detailed in the next
revision of this data sheet.
6.4.4
No SDRAM Configuration
In the case where only the DPU firmware will be used and the on chip SA requirements are
limited to a total of 200 SAs, the SDRAM can be eliminated from the design. This prevents
the eSC from being used for any operations other than using the RMII port to communicate
to the DPU.
Table 6-18 summarizes the DDR signals connections if the DDR interface is not used.
Table 6-18. No SDRAM Configuration
DDR Signal Name
DDR_CONFIG[2:0]
VDDA_DDR_PLL
VSSA_DDR_PLL
VREF_DDR_[2:0]
SDCLK_DIFF_P/N
SDCLK_FB_O
Connection
pull-down (0 ohms to 1 k-ohms)
must be connected to 1.0V
must be connected to ground
0.9V DDR2 Voltage Reference for SSTL bi-directional I/O
open
connect to SDCLK_FB_I through 50-ohm resistor
open
All control signals (includes ODT,
CS_N, RAS_N, CAS_N, WE_N,
BA[2:0], and A[13:0])
DQ[31:0], ECC[6:0]
DM[7:0], ECCDM
DQS[7:0], ECCS
open
open
pull-down (1 k-ohms)
6.5 PLL Interface
The 4450 provides an on-chip phase-locked loop (PLL) to generate clock signals for the
entire chip. The GMII & MII interfaces will normally run from clocks supplied by the
interface, however in certain loss-of-clock conditions they can be driven from internal
clocks as well. The SERDES and SGMII interfaces also run from externally-supplied
reference clocks. The PLL interface signals are all referenced to supply voltage VDDE.
4450 – Data Sheet, DS-0131-06
Page56
Hifn Confidential
EXAR [ EXAR CORPORATION ]
