6.4.1
SDRAM Connection Diagrams
VREF/VTT
GEN.
(VDDQ/2)
DDR VTT
DDR VREF
VDDR
DDR VREF
2
DIFFCLK
1
1
FEEDBACK_CLK
Hifn
4450
23
1
ADDRESS, CONTROL
ODT
DQ[31:16], DQS[3:2], DM[3:2]
DDR2X
16
VDDR (1.8V)
DQ[15:0], DQS[1:0], DM[1:0]
ECC[6:0], ECCS, ECCDM
DDR2X
16
DDR2X
16
Note 1: The total routed length of the
feedback clock matches the DIFFCLK
routed length to the middle SDRAM
device.
DDR_VTT (.9V)
PARALLEL
TERMS
Figure 6-21. SDRAM Connection Diagram
6.4.2
DDR2 Memory Configurations
Table 6-17. DDR2 Memory Configuration
Device Configuration
16 Mbit x 16
Device Capacity
Number of Devices Total Memory
256Mbits / 32MBytes
512Mbits / 64MBytes
1Gbits / 128MBytes
2Gbits / 256MBytes
2
2
2
2
64 MBytes
32 Mbit x 16
128 MBytes
256 MBytes
512 MBytes
64 Mbit x 16
128 Mbit x 16
The standard baseline memory configuration for the eSC running IKE is 64 Mbytes.
However, if support for a large number of SAs is planned, then the larger memory
configurations will be needed.
6.4.3
SDRAM Sizing
Sizing the required external SDRAM is dependent on the system application. The designer
must consider whether,
4450 – Data Sheet, DS-0131-06
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