• External SA storage for the DPU (if additional SAs are required beyond the internal
maximum number)
• eSC Code Storage and data memory (i.e., on-chip IKE)
• DPU/PCP Code Storage (Optional)
The 4450 provides a 32-bit DDR2 SDRAM interface that supports a single 200/400MHz
SDRAM device and storage capacities from 2 MBytes up to 512 MBytes. A 7 bit ECC
interface is optionally supported on the DDR2 SDRAM Interface.
Table 6-17 indicates the supported memory configurations for the DDR SDRAM.
Table 6-16. DDR2 Interface Signal Definition
Pin Name
SDRAM Signal
I/O
out
out
in
Description
sdclk_diff_n
sdclk_diff_p
sdclk_fb_i
CK
SDRAM Clock
CK_N
NA
SDRAM Clock inverted
DDR2 SDRAM De-skew PLL feedback clock
input
sdclk_fb_o
NA
out
DDR2 SDRAM De-skew PLL feedback clock
output
cs_n
CS_N
out
Chip Select (active low)
Row address strobe (active low)
Column address strobe (active low)
Write Enable (active low)
Bank Address
ras_n
RAS_N
CAS_N
WE_N
out
cas_n
out
we_n
out
ba[2]
BA[2]
out
ba[1:0]
a[13]/cke
a[12:0]
dm[3:0]
dqs[3:0]
dq[31:0]
ecc[6:0]
ecc_dm
eccs
BA[1:0]
a[13]
out
Bank Address
out
Address 13/Clock Enable
Address
A[12:0]
DM[3:0]
DQS[3:0]
DQ[31:0]
ECC[6:0]
ECC_DM
ECCS
out
out
Data Mask
in/out
in/out
in/out
out
Data Strobe (one per byte)
Data input/output
ECC data input/output
ECC data mask
in/out
out
ECC strobe
odt
ODT
DDR2 on-die termination control
4450 – Data Sheet, DS-0131-06
Page54
Hifn Confidential
EXAR [ EXAR CORPORATION ]
