PHY
4450
ref_clk
rmii_ref_clk
REF_CLK
CRS_RDV
RDX[1:0]
crs_rdv
rmii_bus1[2]
rxd[1:0]
rmii_bus1[1:0]
txen
rmii_bus0[2]
TXEN
txd[1:0]
rmii_bus0[1:0]
TXD[1:0]
Figure 6-20. RMII MAC Mode
6.3.2
RMII Pin Descriptions (Optional Control Interface)
Table 6-15 contains the pin descriptions for the RMII control port when configured in MAC/
PHY mode.
Table 6-15. 4450 RMII pin descriptions - MAC/PHY mode
Pin Name
RMII-MAC Signal
rmii_ref_clk
I/O
out
in
RMII-PHY Signal
rmii_ref_clk
rmii_txen
I/O
in
Description
rmii_ref_clk
rmii_bus1[2]
Reference Clock
rmii_crs_rdv
in
In MAC mode, Carrier
Sense/Receive data Valid.
In PHY mode, Transmit
enable.
rmii_bus1[1:0]
rmii_bus0[2]
rmii_rxd[1:0]
rmii_txen
in
rmii_txd[1:0]
rmii_crs_rdv
rmii_rxd[1:0]
in
In MAC Mode, Receive
Data.
In PHY mode, Transmit
Data
out
out
out
out
In PHY mode, Carrier
Sense/Receive data Valid.
In MAC mode, Transmit
enable
rmii_bus0[1:0]
rmii_txd[1:0]
In MAC mode, Transmit
Data.
In PHY mode, Receive
Data.
6.4 DDR2 SDRAM Interface
The 4450 DDR2 SDRAM interface is used for:
4450 – Data Sheet, DS-0131-06
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