RGMII/RTBI signaling on the 4450 supports either 1.5V HSTL or 2.5V LVCMOS for both the
host and network interfaces. The dpu_gpio[2]/RGMII/RTBI voltage Level is used to
select can optionally be used to select between 1.5V HSTL or 2.5V LVCMOS if tied high or
low respectively. The voltage selection applies to both host and network sides assuming
they both use one of the RGMII/RTBI interface options.
Boot Rate Select
The Boot Rate Select function allows the user to boot the 4450 Host 0 interface in either
100Mbps or 1Gbps depending on the level of the esc_gpio[2]/100M/1G Boot signal. If
asserted high following reset, the Host 0 port will attempt to boot from the host at
100Mbps. If asserted low, the Host 0 GMAC will boot at 1Gbps.
RMII MAC/PHY Select
The esc_gpio[3]/RMII MAC/PHY signal following reset is used to configure the RMII
Optional Control interface to boot in either PHY or MAC mode if the signal is asserted high
or low following reset.
PHY Interrupt (Optional)
The PHY Interrupt input may be used with Hifn’s Station Management (STM) software to
connect to PHY Interrupts notifying the STM software that an auto negotiation event has
occurred in the PHY.
DDR2 Configuration
In applications using external DDR2 memory, three gpio pins are used for determining
memory sizing and use of On Die Termination (ODT). The dpu_gpio[4:3] pins
(ddr_config_1 and ddr_config_0) are used to select the DDR2 Memory configurations
per the table below. For memory configurations between 64M and 256M, the a[13]\cke
functions as cke (clock enable). For the 512M Byte configuration, the functionality of pin
a[13]\cke is address pin a[13].
Table 6-23. DDR2 Memory Configuration Sizing
Memory Size
64 M Bytes
128 M Bytes
256 M Bytes
512 M Bytes
ddr_config_1
ddr_config_0
0
0
1
1
0
1
0
1
Fiber PHY Control Signals (Optional)
4450 – Data Sheet, DS-0131-06
Page60
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