XR16C2850
LSR BIT-2:
Logic 1 = Enable Xon-Any function. In this mode, any
RX character received will enable Xon.
Logic 0 = No parity error (normal default condition).
Logic 1 = Parity error. The receive character does not
have correct parity information and is suspect. In the
FIFO mode, this error is associated with the character
at the top of the FIFO.
MCR BIT-6:
Logic 0 = Enable Modem receive and transmit input/
output interface (normal default condition).
Logic 1 = Enable infrared IrDA receive and transmit
inputs/outputs. While in this mode, the TX/RX output/
Inputsareroutedtotheinfraredencoder/decoder.The
data input and output levels will conform to the IrDA
infrared interface requirement. As such, while in this
modetheinfraredTXoutputwillbealogic0duringidle
data conditions.
LSR BIT-3:
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not
have a valid stop bit(s). In the FIFO mode this error is
associated with the character at the top of the FIFO.
LSR BIT-4:
MCR BIT-7:
Logic 0 = No break condition (normal default condi-
tion)
Logic 1 = The receiver received a break signal (RX
was a logic 0 for one character frame time). In the
FIFO mode, only one break character is loaded into
the FIFO.
Logic 0 = Divide by one. The input clock (crystal or
external) is divided by sixteen and then presented to
the Programmable Baud Rate Generator (BGR) with-
out further modification, i.e., divide by one (normal,
default condition).
Logic 1 = Divide by four. The divide by one clock
described in MCR bit-7 equals a logic 0, is further
divided by four (also see Programmable Baud Rate
Generator section).
LSR BIT-5:
This bit is the Transmit Holding Register Empty indi-
cator. This bit indicates that the UART is ready to
accept a new character for transmission. In addition,
this bit causes the UART to issue an interrupt to CPU
when the THR interrupt enable is set. The THR bit is
settoalogic1whenacharacteristransferredfromthe
transmit holding register into the transmitter shift
register. The bit is reset to logic 0 concurrently with the
loading of the transmitter holding register by the CPU.
In the FIFO mode, this bit is set when the transmit
FIFO is empty; it is cleared when at least 1 byte is
written to the transmit FIFO.
Line Status Register (LSR)
This register provides the status of data transfers
between. the 2850 and the CPU.
LSR BIT-0:
Logic 0 = No data in receive holding register or FIFO
(normal default condition).
Logic 1 = Data has been received and is saved in the
receive holding register or FIFO.
LSR BIT-6:
LSR BIT-1:
This bit is the Transmit Empty indicator. This bit is set
to a logic 1 whenever the transmit holding register and
the transmit shift register are both empty. It is reset to
logic 0 whenever either the THR or TSR contains a
data character. In the FIFO mode this bit is set to one
wheneverthetransmitFIFOandtransmitshiftregister
are both empty.
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error. A data overrun error occurred
in the receive shift register. This happens when addi-
tional data arrives while the FIFO is full. In this case,
the previous data in the shift register is overwritten.
Note that under this condition, the data byte in the
receive shift register is not transferred into the FIFO;
therefore, the data in the FIFO is not corrupted by the
error.
Rev. 1.00P
24
EXAR [ EXAR CORPORATION ]
