XR16C2850
TRIGGER TABLE-A (Transmit)
Default setting after reset ST16C550 mode
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-3:
BIT-5
BIT-4
FIFO trigger level
Logic 0 = Set DMA mode 0 (normal default condi-
tion).
X
X
None
Logic 1 = Set DMA mode 1.
Transmit operation in mode 0:
TRIGGER TABLE-B (Transmit)
When the 2850 is in the ST16C450 mode (FIFOs
disabled, FCR bit-0 = logic 0) or in the FIFO mode
(FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3 = logic
0) and when there are no characters in the transmit
FIFO or transmit holding register, the -TXRDY pin will
be a logic 0. Once active the -TXRDY pin will go to a
logic 1 after the first character is loaded into the
transmit holding register.
BIT-5
BIT-4
FIFO trigger level
0
0
1
1
0
1
0
1
16
8
24
30
Receive operation in mode 0:
TRIGGER TABLE-C (Transmit)
When the 2850 is in mode 0 (FCR bit-0 = logic 0) or
in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 =
logic 0) and there is at least one character in the
receive FIFO, the -RXRDY pin will be a logic 0. Once
active the -RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
BIT-5
BIT-4
FIFO trigger level
0
0
1
1
0
1
0
1
8
16
32
56
Transmit operation in mode 1:
When the 2850 is in FIFO mode ( FCR bit-0 = logic 1,
FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1
when the transmit FIFO is completely full. It will be a
logic 0 if one or more FIFO locations are empty.
TRIGGER TABLE-D (Transmit)
BIT-5
BIT-4
FIFO trigger level
Receive operation in mode 1:
X
X
User programmable
Trigger levels
When the 2850 is in FIFO mode (FCR bit-0 = logic 1,
FCR bit-3 = logic 1) and the trigger level has been
reached, or a Receive Time Out has occurred, the -
RXRDY pin will go to a logic 0. Once activated, it will
go to a logic 1 after there are no more characters in the
FIFO.
FCR BIT 6-7: (logic 0 or cleared is the default condi-
tion, RX trigger level =8)
These bits are used to set the trigger level for the
receiver FIFO interrupt. The FCTR Bits 4-5 selects
one of the following table.
FCR BIT 4-5: (logic 0 or cleared is the default condi-
tion, TX trigger level = none)
The XR16C2850 provide 4 user selectable trigger
levels. The FCTR Bits 4-5 selects one of the following
tables. These bits are used to set the trigger level for
thetransmitFIFOinterrupt. TheXR16C2850willissue
a transmit empty interrupt when the number of char-
acters in FIFO drops below the selected trigger level.
Rev. 1.00P
20
EXAR [ EXAR CORPORATION ]
