XR16C2850
LCR BIT-3:
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break
condition.
Parity or no parity can be selected via this bit.
Logic 0 = No parity (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
LCR BIT-7:
The internal baud rate counter latch and Enhance
Feature mode enable.
LCR BIT-4:
Logic 0 = Divisor latch disabled (normal default con-
dition).
Logic 1 = Divisor latch and enhanced feature register
enabled.
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1s in the transmitted data. The
receiver must be programmed to check the same
format. (normal default condition)
Modem Control Register (MCR)
Logic 1 = EVEN Parity is generated by forcing an even
thenumberoflogic1sinthetransmitted. Thereceiver
must be programmed to check the same format.
This register controls the interface with the modem or
a peripheral device.
MCR BIT-0:
LCR BIT-5:
Logic 0 = Force -DTR output to a logic 1 (normal
default condition).
Logic 1 = Force -DTR output to a logic 0.
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
LCR BIT-5 = logic 0, parity is not forced (normal
default condition).
MCR BIT-1:
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit
is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit
is forced to a logical 0 for the transmit and receive
data.
Logic 0 = Force -RTS output to a logic 1 (normal
default condition).
Logic 1 = Force -RTS output to a logic 0.
Automatic RTS may be used for hardware flow control
by enabling EFR bit-6 (see EFR bit-6).
MCR BIT-2:
Internal loop back mode only.
Logic 0 = Set -OP1 output to a logic 1. (normal default
condition)
LCR
LCR
LCR
Parity selection
Bit-3 Bit-4 Bit-5
Logic 1 = Set -OP1 output to a logic 0.
0
1
1
1
1
X
0
1
0
1
X
0
0
1
1
No parity
Odd parity
Even parity
Force parity 1
Forced parity 0
MCR BIT-3:
Logic 0 = Forces INT outputs to three state mode
(normal default condition).
Logic 1 = Forces the INT outputs to the active mode.
MCR BIT-4:
LCR BIT-6:
Logic 0 = Disable loopback mode (normal default
condition).
Logic 1 = Enable local loopback mode (diagnostics).
When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
MCR BIT-5:
Logic 0 = No TX break condition (normal default
condition).
Logic 0 = Disable Xon-Any function (for 16C550
compatibility, normal default condition).
Rev. 1.00P
23
EXAR [ EXAR CORPORATION ]
