XR16C2850
TRIGGER TABLE-A (Receive)
Interrupt Status Register (ISR)
Default setting after reset ST16C550 mode
The 2850 provides six levels of prioritized interrupts to
minimize external software interaction. The Interrupt
Status Register (ISR) provides the user with six inter-
ruptstatusbits. PerformingareadcycleontheISRwill
provide the user with the highest pending interrupt
level to be serviced. No other interrupts are acknowl-
edged until the pending interrupt is serviced. When-
ever the interrupt status register is read, the interrupt
status is cleared. However it should be noted that only
the current pending interrupt is cleared by the read. A
lower level interrupt may be seen after rereading the
interruptstatusbits.TheInterruptSourceTable.Table
6, shows the data values (bit 0-5) for the six prioritized
interrupt levels and the interrupt sources associated
with each of these interrupt levels:
BIT-7
BIT-6
FIFO trigger level
0
0
1
1
0
1
0
1
1
4
8
14
TRIGGER TABLE-B (Receive)
BIT-7
BIT-6
FIFO trigger level
0
0
1
1
0
1
0
1
8
16
24
28
TRIGGER TABLE-C (Receive)
BIT-7
BIT-6
FIFO trigger level
0
0
1
1
0
1
0
1
8
16
56
60
TRIGGER TABLE-D (Receive)
BIT-7
BIT-6
FIFO trigger level
X
X
User programmable
Trigger levels
Rev. 1.00P
21
EXAR [ EXAR CORPORATION ]
