XR16C2850
LSR BIT-7:
Flow control, when enabled, allows the starting and
stopping of the transmissions based on the external
modem -CTS signal. A logic 1 at the -CTS pin will stop
2850 transmissions as soon as current character has
finished transmission.
Logic 0 = No Error (normal default condition).
Logic 1 = At least one parity error, framing error or
break indication is in the current FIFO data. This bit is
cleared when LSR register is read and there are no
subsequent errors in the FIFO.
Normally MSR bit-4 bit is the compliment of the -CTS
input. However, in the loopback mode, this bit is
equivalent to the RTS bit in the MCR register.
Modem Status Register (MSR)
This register provides the current state of the control
interface signals from the modem, or other peripheral
device that the 2850 is connected to. Four bits of this
register are used to indicate the changed information.
These bits are set to a logic 1 whenever a control input
from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
MSR BIT-5:
DSR (active high, logical 1). Normally this bit is the
compliment of the -DSR input. In the loopback mode,
thisbitisequivalenttotheDTRbitintheMCRregister.
MSR BIT-6:
RI (active high, logical 1). Normally this bit is the
compliment of the -RI input. In the loopback mode this
bit is equivalent to the OP1 bit in the MCR register.
MSR BIT-0:
Logic 0 = No -CTS Change (normal default condition).
Logic 1 = The -CTS input to the 2850 has changed
state since the last time it was read. A modem Status
Interrupt will be generated.
MSR BIT-7:
CD (active high, logical 1). Normally this bit is the
compliment of the -CD input. In the loopback mode
this bit is equivalent to the OP2 bit in the MCR register.
MSR BIT-1:
Scratchpad Register (SPR)
Logic 0 = No -DSR Change (normal default condition).
Logic 1 = The -DSR input to the 2850 has changed
state since the last time it was read. A modem Status
Interrupt will be generated.
TheXR16C2850providesatemporarydataregisterto
store 8 bits of user information.
Enhanced Feature Register (EFR)
MSR BIT-2:
Logic 0 = No -RI Change (normal default condition).
Logic 1 = The -RI input to the 2850 has changed from
a logic 0 to a logic 1. A modem Status Interrupt will be
generated.
Enhanced features are enabled or disabled using this
register.
Bits-0 through 4 provide single or dual character
software flow control selection. When the Xon1 and
Xon2 and/or Xoff1 and Xoff2 modes are selected (see
Table 7), the double 8-bit words are concatenated into
two sequential characters.
MSR BIT-3:
Logic 0 = No -CD Change (normal default condition).
Logic 1 = Indicates that the -CD input has changed
state since the last time it was read. A modem Status
Interrupt will be generated.
EFR BIT 0-3: (logic 0 or cleared is the default condi-
tion)
Combinations of software flow control can be selected
by programming these bits.
MSR BIT-4:
-CTS functions as hardware flow control signal input if
it is enabled via EFR bit-7. The transmit holding
register flow control is enabled/disabled by MSR bit-4.
Rev. 1.00P
25
EXAR [ EXAR CORPORATION ]
