XR16C2850
TRIGGER LEVEL / FIFO DATA COUNT REGISTER
User programmable transmit / receive trigger level
register.
XR16C2850 EXTERNAL RESET CONDITIONS
REGISTERS
RESET STATE
TRG BIT 0-7: Write only.
These bits are used to program desire trigger levels
that are not available in standard tables.
IER
ISR
IER BITS 0-7 = logic 0
ISR BIT-0=1, ISR BITS 1-7 =
logic 0
LCR, MCR
LSR
BITS 0-7 = logic 0
TRG BIT 0-7: Read only.
LSR BITS 0-4 = logic 0,
LSR BITS 5-6 = logic 1 LSR, BIT
7 = logic 0
MSR BITS 0-3 = logic 0,
MSR BITS 4-7 = logic levels of
the input signals
Transmit / receive FIFO count. Number of characters
in transmit or receive FIFO can be read via this
register.
MSR
ENHANCED MODE SELECT REGISTER
This register is accessible only when FCTR Bit-6 is set
to 1.
FCR, EFR
FCTR
EMSR
BITS 0-7 = logic 0
BITS 0-7= logic 0
BITS 0-7 = logic 0
EMSR BIT-0: Write only
0 = Receive FIFO count register. The scratch pad
register is used to provide the receive FIFO count
when it is read.
SIGNALS
RESET STATE
1 = Transmit FIFO count register. The scratch pad
register is used to provide the transmit FIFO count
when it is read.
TX
Logic 1
Logic 1
Logic 1
Logic 1
Logic 1
Logic 0
Logic 0
-OP2
-RTS
-DTR
-RXRDY
-TXRDY
INT
EMSR BIT-1: Write only
0 = Normal.
1 = Alternate receive - transmit FIFO count. When
EMSR Bit-0=1 and EMSR Bit=1, scratch pad register
is used to provide the receive - transmit FIFO count
when it is read every alternate read cycle. The TRG
Bit-7 will provide the FIFO count mode information,
TRG Bit-7=0 receive mode, TRG Bit-7=1 transmit
mode.
EMSR BIT 4-7:
Reserved for future use.
Rev. 1.00P
28
EXAR [ EXAR CORPORATION ]
