XR16C2850
Table 6, INTERRUPT SOURCE TABLE
Priority
Level
[ ISR BITS ]
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Source of the interrupt
1
2
2
3
4
5
6
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xoff signal)/ Special character
CTS, RTS change of state
ISR BIT-0:
LCR BIT 0-1: (logic 0 or cleared is the default condi-
tion)
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
These two bits specify the word length to be transmit-
ted or received.
Logic 1 = No interrupt pending (normal default condi-
tion).
BIT-1
BIT-0
Word length
ISRBIT1-3:(logic0orclearedisthedefaultcondition)
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, and 3 (see Interrupt
Source Table).
0
0
1
1
0
1
0
1
5
6
7
8
ISRBIT4-5:(logic0orclearedisthedefaultcondition)
These bits are enabled when EFR bit-4 is set to a logic
1. ISR bit-4 indicates that matching Xoff character(s)
have been detected. ISR bit-5 indicates that CTS,
RTS have been generated. Note that once set to a
logic 1, the ISR bit-4 will stay a logic 1 until Xon
character(s) are received.
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in
conjunction with the programmed word length.
BIT-2
Word length
Stop bit
length
ISRBIT6-7:(logic0orclearedisthedefaultcondition)
These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFOs
are enabled
(Bit time(s))
0
1
1
5,6,7,8
5
6,7,8
1
1-1/2
2
Line Control Register (LCR)
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
Rev. 1.00P
22
EXAR [ EXAR CORPORATION ]
